In manufacturing semiconductor devices, care is taken to ensure that parasitic transistors do not activate under normal operating conditions. A parasitic transistor is an unwanted transistor located at adjacent active device regions. In particular, a parasitic thick field MOSFET is formed when the silicon interfacial layer underlying the field oxide insulator is inverted, either from unwanted dopants of opposite conductivity type to the bulk region residing at the interface, or by formation of a channel region (MOSFET) due to voltages on poly or metal leads formed on top of the field oxide. For example, parasitic thick field MOSFET transistors in CMOS or BiCMOS semiconductor devices may be found between N+ moats of adjacent NMOS devices, which have a P- well region therebetween; between an N+ moat and a nearby N- well, which may have a P- well therebetween; between P+ moats of adjacent PMOS devices, which have an N- well region therebetween, or between a P+ moat and a nearby P- well, which may have a N- well region therebetween. In each case, electrical fields created by signals on conductors overlying such parasitic transistors may potentially invert "parasitic channels" and cause such parasitic transistors to conduct.
Various techniques are known to those skilled in the art for ensuring that such parasitic transistors do not activate under normal operating conditions. For example, the further apart active, nonparasitic, transistors are from one another, or the more vertically spaced apart a conductive region is from a parasitic channel, the less likely it is for a parasitic transistor to activate. However, it is desirable in the manufacture of semiconductor devices to compact more nonparasitic, active transistors into a smaller area. Consequently, the isolation problem becomes more acute as semiconductor device density increases.
Some manufacturing processes currently use a P type channel stop implant to help deactivate parasitic transistors. When an oxide layer, such as a field oxide, is thermally grown over parasitic channel region, a portion of the P dopant in the parasitic channel region tends to segregate into the oxide and thereby deplete the P doping of the parasitic channel region under the oxide. This depleted region can easily be inverted by signals present on overlying conductive layers because it is lightly doped after the segregation of P type dopant into the oxide. Consequently, the P type channel stop implant is configured to add a quantity of P type dopant into such regions to compensate for the depletion. The increased dopant causes the threshold voltage associated with the parasitic channel to increase and the parasitic transistor to remain substantially deactivated under normal operating conditions.
This P channel stop implant may also be implanted into N well regions to simplify fabrication of CMOS devices. N type dopant, in contrast to P type dopant, tends to "pile-up" at the substrate surface where a field oxide is thermally grown. This pile-up phenomenon increases the concentration of N type dopant at this surface. The small dosage of P type channel stop dopant conventionally implanted in the N well regions does not significantly compensate this piled-up region. Therefore, a conventional parasitic transistor having this piled-up N well region as a parasitic channel tends to remain substantially deactivated during normal operating conditions.
However, as device geometries shrink, the effectiveness of this pile-up region in deactivating such a parasitic transistor diminishes because there is less pile-up. With smaller geometries, a greater dosage of P type channel stop dopant may be used to deactivate parasitic transistors having P type parasitic channel regions. As this P type channel stop dopant is simultaneously implanted into N well regions, it tends to more completely compensate the N dopant in the N well regions in spite of the pile up phenomenon. Consequently, lowered threshold voltage is required to invert this N type region. Moreover, as device geometries shrink, the thickness of field oxide regions shrinks as well. As the field oxide thickness shrinks, conductors overlying the field oxide region tend to reside closer to the parasitic channel region. Electric fields resulting from signals on such conductors increase in this N type region, and therefore, greater threshold voltages are present to invert the N region and form a P type parasitic channel.
One solution to this isolation problem could be to block implantation of P type channel stop dopant into N type well regions. However, this solution is undesirable because it requires the use of an additional masking step. Consequently, a need exists for a method of isolating active transistors from one another without adding masking steps.